Reset has four sources on the LPC2364/66/68: the RESET pin, the Watchdog Reset,
Power On Reset (POR) and the Brown Out Detection circuit (BOD). The RESET pin is a
Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating
voltage attains a usable level, starts the Wake-up timer (see description in Section 7.24.3
“Wake-up timer”), causing reset to remain asserted until the external Reset is
de-asserted, the oscillator is running, a fixed number of clocks have passed, and the
Flash controller has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
7.25.2 Brown-out detection
The LPC2364/66/68 includes 2-stage monitoring of the voltage on the VDD pins. If this
voltage falls below 2.95 V, the Brown-Out Detector (BOD) asserts an interrupt signal to
the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt
Enable Register in the VIC in order to cause a CPU interrupt; if not, software can monitor
the signal by reading a dedicated status register.
The second stage of low-voltage detection asserts Reset to inactivate the LPC2364/66/68
when the voltage on the VDD pins falls below 2.65 V. This Reset prevents alteration of the
Flash as operation of the various elements of the chip would otherwise become unreliable
due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point
the Power-On Reset circuitry maintains the overall Reset.